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The ST16C654/654D1 (654) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 64 bytes of transmit and receive FIFOs, transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 1.5 Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. Selectable interrupt polarity provides flexibility to meet design requirements. An internal loopback capability allows onboard diagnostics. The 654 is available in 64 pin TQFP 68 , pin PLCC and 100 pin QFP packages. The 64 pin package only offers the 16 mode interface, but the 68 and 100 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The ST16C654CQ64 (64 pin) offers three state interrupt output while the ST16C654DCQ64 provides continuous interrupt output. The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The ST16C654/654D is compatible with the industry standard ST16C454 and ST16C654/554D.
NOTE:
1 Covered by U.S. Patent #5,649,122.

OCTOBER 2003
A2:A0 D7:D0 IOR# IOW# CSA# CSB# CSC# CSD# INTA INTB INTC INTD CHCCLK TXRDY# A-D RXRDY# A-D Reset 16/68# INTSEL CLKSEL
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
GENERAL DESCRIPTION
FEATURES
* Pin-to-pin compatible with ST16C454, ST16C554
and TI's TL16C554AFN and TL16C754BFN
* Intel or Motorola Data Bus Interface select * Four independent UART channels
s s s s s s s s s s
Register Set Compatible to 16C550 Data rates of up to 1.5 Mbps 64 Byte Transmit FIFO 64 Byte Receive FIFO with error tags 4 Selectable TX and RX FIFO Trigger Levels Automatic Hardware (RTS/CTS) Flow Control Automatic Software (Xon/Xoff) Flow Control Progammable Xon/Xoff characters Wireless Infrared (IrDA 1.0) Encoder/Decoder Full modem interface
* 2.97V to 5.5V supply operation * Sleep Mode (200 uA typical) * Crystal oscillator or external clock input
APPLICATIONS
* * * * *
Portable Appliances Telecommunication Network Routers Ethernet Network Routers Cellular Data Devices Factory Automation and Process Controls
FIGURE 1. ST16C654 BLOCK DIAGRAM
2.97V to 5.5V VCC GND UART Channel A 64 Byte TX FIFO UART Regs BRG TX & RX IR ENDEC 64 Byte RX FIFO
TXA, RXA, IRTXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA#
Data Bus Interface
UART Channel B (same as Channel A) UART Channel C (same as Channel A) UART Channel D (same as Channel A)
TXB, RXB, IRTXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB# TXC, RXC, IRTXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# TXD, RXD, IRTXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# XTAL1 XTAL2
Crystal Osc/Buffer
654 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538* (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
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FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE
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REV. 5.0.0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND TQFP PACKAGES
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ORDERING INFORMATION
ST16C654CQ64
ST16C654CJ68
ST16C654IQ64
ST16C654IJ68
PART NUMBER
64-Lead TQFP -40C to +85C
68-Lead PLCC -40C to +85C
68-Lead PLCC
64-Lead TQFP
PACKAGE
OPERATING TEMPERATURE RANGE
0C to +70C
0C to +70C
DEVICE STATUS
Active
Active
Active
Active
3
ST16C654DCQ64 ST16C654CQ100 ST16C654DIQ64 PART NUMBER ST16C654IQ100 64-Lead TQFP 64-Lead TQFP 100-Lead QFP 100-Lead QFP PACKAGE -40C to +85C -40C to +85C OPERATING TEMPERATURE RANGE 0C to +70C 0C to +70C DEVICE STATUS Active Active Active Active
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PIN DESCRIPTIONS
Pin Description
NAME 64-TQFP 68-PLCC 100-QFP TYPE PIN# PIN # PIN # DESCRIPTION

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# (VCC) IOW# (R/W#) CSA# (CS#) CSB# (A3) CSC# (A4) CSD# (VCC)
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
DATA BUS INTERFACE 22 23 24 60 59 58 57 56 55 54 53 40 32 33 34 5 4 3 2 1 68 67 66 52 37 38 39 95 94 93 92 91 90 89 88 66 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transaction. Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used and should be connected to VCC. When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the Motorola bus interface. When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is at logic 0, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. When 16/68# pin is at logic 1, this input is chip select C (active low) to enable channel C in the device. When 16/68# pin is at logic 0, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. When 16/68# pin is at logic 1, this input is chip select D (active low) to enable channel D in the device. When 16/68# pin is at logic 0, this input is not used and should be connected VCC.
9
18
15
I
7
16
13
I
11
20
17
I
38
50
64
I
42
54
68
I
4
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Pin Description
NAME INTA (IRQ#) 64-TQFP 68-PLCC 100-QFP TYPE PIN# PIN # PIN # 6 15 12 DESCRIPTION
INTSEL
-
65
87
I
Interrupt Select (active high, input with internal pull-down). When 16/68# pin is at logic 1 for Intel bus interface, this pin can be used in conjunction with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3 and enable the interrupt outputs. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and disable the interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output. See MCR bit-3 description for full detail. This pin must be at logic 0 in the Motorola bus interface mode. Due to pin limitations on 64 pin packages, this pin is not available. To cover this limitation, two 64 pin TQFP packages versions are offered. This pin is bonded to VCC internally in the ST16C654D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the ST16C654 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. UART channels A-D Transmitter Ready (active low). The outputs provide the TX FIFO/THR status for transmit channels A-D. See Table 5. If these outputs are unused, leave them unconnected.
TXRDYA# TXRDYB# TXRDYC# TXRDYD# RXRDYA# RXRDYB# RXRDYC# RXRDYD# TXRDY#
-
39
5 25 56 81 100 31 50 82 45
O
O
UART channels A-D Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channels A-D. See Table 5. If these outputs are unused, leave them unconnected.
O
Transmitter Ready (active low). This output is a logically ANDed status of TXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See Table 5. If this output is unused, leave it unconnected.
RXRDY#
-
38
44
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21 49 55
18 63 69
O
When 16/68# pin is at logic 1 for Intel bus interface, these ouputs become the interrupt outputs for channels B, C, and D.
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O When 16/68# pin is at logic 1 for Intel bus interface, this ouput (OD) becomes channel A interrupt output.
When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation.
When 16/68# pin is at logic 0 for Motorola bus interface, these outputs are unused and will stay at logic zero level. Leave these outputs unconnected.
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DSRA# DSRB# DSRC# DSRD#
1 17 32 48
10 26 44 60
7 23 58 74
I
UART channels A-D Carrier-Detect (active low) or general purpose input.
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3 15 34 46
12 24 46 58
9 21 60 72
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11 25 45 59
8 22 59 73
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Pin Description
NAME FSRS# 64-TQFP 68-PLCC 100-QFP TYPE PIN# PIN # PIN # 76 I MODEM OR SERIAL I/O INTERFACE TXA TXB TXC TXD 8 10 39 41 17 19 51 53 14 16 65 67 O IRTXA IRTXB IRTXC IRTXD RXA RXB RXC RXD RTSA# RTSB# RTSC# RTSD# 62 20 29 51 5 13 36 44 7 29 41 63 14 22 48 56 6 24 57 75 97 34 47 85 11 19 62 70 O I O
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
DESCRIPTION FIFO Status Register Select (active low input with internal pull-up). The content of the FSTAT register is placed on the data bus when this pin becomes active. However it should be noted, D0-D3 contain the inverted logic states of TXRDY# A-D pins, and D4-D7 the logic states (un-inverted) of RXRDY# A-D pins. A valid address is not required when reading this status register.
UART channels A-D Transmit Data and infrared transmit data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. UART channel A-D Infrared Transmit Data. The inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. Regardless of the logic state of MCR bit-6, this pin will be operating in the Infrared mode. UART channel A-D Receive Data or infrared receive data. Normal receive data input must idle at logic 1 condition.
6
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Pin Description
NAME RIA# RIB# RIC# RID# 64-TQFP 68-PLCC 100-QFP TYPE PIN# PIN # PIN # 63 19 30 50 8 28 42 62 98 33 48 84 I DESCRIPTION
UART channels A-D Ring-Indicator (active low) or general purpose input.
ANCILLARY SIGNALS XTAL1 XTAL2 16/68# 25 26 35 36 31 40 41 36 I O I Crystal or external clock input. Crystal or buffered clock output. Intel or Motorola Bus Select (input with internal pull-up). When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is at logic 0, 68 or Motorola mode, the device will operate in the Motorola bus type of interface. Motorola bus interface is not available on the 64 pin package. Baud-Rate-Generator Input Clock Prescaler Select for channels AD. This input is only sampled during power up or a reset. Connect to VCC for divide by 1 (default) and GND for divide by 4. MCR[7] can override the state of this pin following a reset or initialization. See MCR bit-7 and Figure 6 in the Baud Rate Generator section. This input provides the clock for UART channel C. An external 16X baud clock or the crystal oscillator's output, XTAL2, must be connected to this pin for normal operation. This input may also be used with MIDI (Musical Instrument Digital Interface) applications when an external MIDI clock is provided. This pin is only available in the 100-pin QFP package. When 16/68# pin is at logic 1 for Intel bus interface, this input becomes the
CLKSEL
21
30
35
I
CHCCLK
-
-
42
I
Motorola bus interface is not available on the 64 pin package. VCC GND N.C. 4, 35, 52 14, 28, 45, 61 13, 47, 64 6, 23, 40, 57 10, 61, 86 20, 46, 71, 96 1- 4, 2628, 29, 30, 5155, 77, 78, 79, 80
Pwr 2.97V to 5.5V power supply. The inputs are not 5V tolerant when operating at 3.3V. Pwr Power supply common, ground. No Connection. These pins are not used in either the Intel or Motorola bus modes. These pins are open, but typically, should be connected to GND for good design practice.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
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37
43
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integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 1.5 Mbps. The ST16C654 can operate from 2.97 to 5.5 volts. The 654 is fabricated with an advanced CMOS process.
The rich feature set of the 654 is available through the internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations for the 64 pin 654 this feature is offered by two different TQFP packages. The ST16C654DCV operates in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C654CV operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND. The ST16C654 offers a clock prescaler select pin to allow system/board designers to preset the default baud rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator. It can then be overridden following initialization by MCR bit-7. The 100 pin packages offer several other enhanced features. These features include a CHCCLK clock input, FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels. The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for Infrared applications. These outputs are provided in addition to the standard asynchronous modem data outputs.
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Enhanced FIFO The 654 QUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 16 bytes in the ST16C554, or one byte in the ST16C454. The 654 is designed to work with high performance data communication systems, that require fast data processing time. Increased performance is realized in the 654 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the 654, the data buffer will not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU's bandwidth requirement, increases performance, and reduces power consumption. Data Rate The 654 is capable of operation up to 1.5 Mbps at 5V with 16x internal sampling clock rate. The device can operate at 5V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 24 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for data rates of up to 921.6 kbps. Enhanced Features

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
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The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 654 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4.

REV. 5.0.0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
2.1
2.0 FUNCTIONAL DESCRIPTIONS
CPU Interface
9
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The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset function in the device. Following a power-on reset or an external reset, the 654 is software compatible with previous generation of UARTs, 16C454 and 16C554. 2.3 Channel Selection
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2.2
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Device Reset
TABLE 1: CHANNEL A-D SELECT IN 16 MODE
CSA CSB CSC CSD # # # # 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 0 FUNCTION UART de-selected Channel A selected Channel B selected Channel C selected Channel D selected Channels A-D selected
During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for connection with Motorola, and other popular microprocessor bus types. In this mode the 654 decodes two additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode function is used only when in the Motorola Bus Mode. See Table 2.
TABLE 2: CHANNEL A-D SELECT IN 68 MODE
CS# 1 0 0 0 0 A4 N/A 0 0 1 1 A3 N/A 0 1 0 1 FUNCTION UART de-selected Channel A selected Channel B selected Channel C selected Channel D selected
10
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
2.4
Channels A-D Internal Registers
Each UART channel in the 654 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratchpad register (SPR). Beyond the general 16C550 features and capabilities, the 654 offers enhanced feature registers (EFR, Xon/ Xoff 1, Xon/Xoff 2, FSTAT) that provide automatic RTS and CTS hardware flow control and automatic Xon/Xoff software flow control. All the register functions are discussed in full detail later in "Section 3.0, UART INTERNAL REGISTERS" on pag e22. 2.5 INT Ouputs for Channels A-D The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figure 20 through 25.
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCR BIT-0 = 1 (FIFO ENABLED) FCR BIT-0 = 0 (FIFO DISABLED) INT Pin 0 = a byte in THR 1 = THR empty FCR Bit-3 = 0 (DMA Mode Disabled) 0 = FIFO above trigger level 1 = FIFO below trigger level or FIFO empty FCR Bit-3 = 1 (DMA Mode Enabled) 0 = FIFO above trigger level 1 = FIFO below trigger level or FIFO empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) INT Pin 0 = no data 1 = 1 byte 0 = FIFO below trigger level 1 = FIFO above trigger level FCR Bit-3 = 1 (DMA Mode Enabled) 0 = FIFO below trigger level 1 = FIFO above trigger level
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not mean "direct memory access" but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFOs are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 654 is placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show their behavior. Also see Figure 20 through 25.
11

The 654 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see "Section 2.8, Programmable Baud Rate Generator" on page 12 FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS
R = 300 K to 4 0 0 K
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown in Figure 5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. For further reading on oscillator circuit please see application note DAN108 on EXAR's web site. 2.8 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.

PINS FCR BIT-0=0 (FIFO DISABLED) RXRDY# 0 = 1 byte 1 = no data 0 = THR empty 1 = byte in THR TXRDY#
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D
FCR BIT-0=1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) 0 = at least 1 byte in FIFO 1 = FIFO empty 0 = FIFO empty 1 = at least 1 byte in FIFO FCR Bit-3 = 1 (DMA Mode Enabled) 1 to 0 transition when FIFO reaches the trigger level, or timeout occurs. 0 to 1 transition when FIFO empties. 0 = FIFO has at least 1 empty location. 1 = FIFO is full.
2.7
Crystal Oscillator or External Clock Input
X T A L1
14 .74 56 M Hz
X T A L2
C1 22 -47 pF
C2 22 -47 pF
12
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
DLL and DLM R e g is te rs P re s c a le r D iv id e b y 1 XTAL1 XTAL2 C ry s ta l O sc/ B u ffe r P re s c a le r D iv id e b y 4 M C R B it-7 =0 (d e fa u lt) B a u d R a te G e n e ra to r L o g ic M C R B it-7 =1
16X S a m p lin g R a te C lo c k to T ra n s m itte r
Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x MCR Bit-7=1 MCR Bit-7=0 Clock (Decimal) Clock (HEX) (DEFAULT) 100 600 1200 2400 4800 9600 19.2k 38.4k 57.6k 115.2k 230.4k 400 2400 4800 9600 19.2k 38.4k 76.8k 153.6k 230.4k 460.8k 921.6k 2304 384 192 96 48 24 12 6 4 2 1 900 180 C0 60 30 18 0C 06 04 02 01 DLM PROGRAM VALUE (HEX) 09 01 00 00 00 00 00 00 00 00 00 DLL PROGRAM VALUE (HEX) 00 80 C0 60 30 18 0C 06 04 02 01 DATA RATE ERROR (%) 0 0 0 0 0 0 0 0 0 0 0
2.9
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location.
13

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transm it S hift Register (TSR)
TX NOF IFO1
2.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
RX FIFO
5 +7
Data B yte
THR Interrupt (ISR bit-1) falls below the program m ed Trigger Level and then when becomes em pty. FIFO is Enabled by FCR bit-0=1 A uto CTS Flow Control (CTS# pin) Flow Control Characters (X off1/2 and Xon1/2 Reg. A uto Software Flow Control
16X Clock
Transm it Data S hift Register (TSR)
2 ), ); 7
14
B S L
B S M

2.9.2
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Transmitter Operation in non-FIFO Mode
Data Byte
Transm it Holding Register (THR)
THR Interrupt (IS R bit-1) Enabled by IER bit-1
16X Clock
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
2.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. 2.10.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock Receive Data Shift Register (RSR) Data Bit Validation
Receive Data Characters
Receive Data Byte and Errors
Receive Data Holding Register (RHR)
RHR Interrupt (ISR bit-2)
15

2),);5
VWLE 56/ QL VJD7 URUU(
Error Tags (64-sets)
Error Tags in LSR bits 4:2
2.11
Auto RTS Hardware Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see Figure 11):
* Enable auto RTS flow control using EFR bit-6. * The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If needed, the RTS interrupt can be enabled through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1. 2.12 Auto CTS Flow Control Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific application requirement (see Figure 11):
* Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-asserted (logic 0), indicating more data may be sent.
16
2), ) ;5

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock Receive Data Shift Register (RSR) Data Bit Validation
Receive Data Characters
64 bytes by 11-bit wide FIFO
Exam ple : - RX FIFO trigger level selected at 16 bytes Data falls to 8
Receive Data FIFO
RTS# re-asserts when data falls below the flow control trigger level to restart rem ote transmitter. Enable by EFR bit-6=1, MCR bit-1. RHR Interrupt (ISR bit-2) programm ed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1.
FIFO Trigger=16
Data fills to 56
Receive Data Byte and Errors
Receive Data
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REV. 5.0.0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
INTA (RXA FIFO Interrupt)
CTSB#
RXA FIFO
RTSA#
TXB
Receiver FIFO Trigger Reached
SELECTED TRIGGER INT PIN ACTIVATION LEVEL
Auto RTS Trigger Level
Local UART UARTA
Transmitter
Auto CTS Monitor
Data Starts
60
56
16
Receive Data
8
Assert RTS# to Begin Transmission 1 ON
2
RX FIFO Trigger Level
3
TABLE 7: AUTO RTS/CTS FLOW CONTROL
4
RTSA#
TXA
CTSA#
RXA
ON
60
56
16
8
5
7
RTS High Threshold
17
6 8
RTS# PIN DE-ASSERTED (LOGIC 1)
OFF
Suspend
OFF
16
60 60 56
RTSB# CTSB# RTS Low Threshold RXB TXB Restart 9 10 11 ON
RTS# PIN RE-ASSERTED (LOGIC 0)
Receiver FIFO Trigger Reached
Remote UART UARTB
Auto RTS Trigger Level
12
Auto CTS Monitor
Transmitter
56 16
ON
0
RX FIFO Trigger Level
8
When software flow control is enabled (See Table 15), the 654 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 654 will halt transmission (TX) as soon as the current character has completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output pin will be activated. Following a suspension due to a match of the Xoff character, the 654 will monitor the receive data stream for a match to the Xon-1,2 character. If a match is found, the 654 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/ Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 654 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the 654 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 654 sends the Xoff1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive FIFO crosses the programmed trigger level. To clear this condition, the 654 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed trigger level. Table 8 below explains this. TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal incoming RX data. The 654 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character.
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2.14
Special Character Detect
18

2.13

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Auto Xon/Xoff (Software) Flow Control
INT PIN ACTIVATION
XOFF CHARACTER(S) SENT (CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT (CHARACTERS IN RX FIFO)
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
2.15
Infrared Mode
The 654 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGHpulse for each "0" bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 12 below. The infrared encoder and decoder are enabled by setting MCR register bit-6 to a `1'. When the infrared feature is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 12. Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
C haracter Start D ata Bits 1 0 1 0 0 1 1 0 Stop
T X D ata
0
1
T ransm it IR Pulse (T X Pin) B it T im e 3/16 B it T im e
1/2 B it T im e
IrEncoder-1
Receive IR Pulse (RX pin)
Bit Time 1/16 Clock Delay
RX Data
0 Start
1
0
1
0
0
1
1
0
1 Stop
Data Bits Character
IRdecoder-1
19

The 654 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for the 654 to enter sleep mode: s no interrupts pending for all four channels of the 654 (ISR bit-0 = 1) s sleep mode of both channels are enabled (IER bit-4 = 1) s modem inputs are not toggling (MSR bits 0-3 = 0) s RX input pins are idling at a logic 1 The 654 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has entered the sleep mode. The 654 resumes normal operation by any of the following: s a receive data start bit transition (logic 1 to 0) s a data byte is loaded to the transmitter, THR or FIFO s a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI# If the 654 is awakened by any one of the above conditions, it will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. If the 2750 is awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending from any channel. The 654 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0. If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain steady when the 654 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical Characteristics on page 37. If the input lines are floating or are toggling while the 654 is in sleep mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer would be required to keep the address, data and control lines steady to achieve the low current. A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few receive characters may be lost. Also, make sure the RX A-D pins are idling at logic 1 or "marking" condition during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another type) are also put to sleep mode and cannot maintain the "marking" condition. To avoid this, the system design engineer can use a 47k ohm pull-up resistor on each of the RX A-D inputs. 2.17 Internal Loopback The 654 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback test else upon exiting the loopback test the UART may detect and report a false "break" signal.

2.16
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
Sleep Mode with Auto Wake-Up
20
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC Transmit Shift Register (THR/FIFO) MCR bit-4=1 Internal Data Bus Lines and Control Signals Receive Shift Register (RHR/FIFO) VCC RTS# A-D Modem / General Purpose Control Logic RTS# TX A-D
RX A-D
CTS# VCC DTR#
CTS# A-D DTR# A-D
DSR# OP1# RI# OP2# CD#
DSR# A-D
RI# A-D CD# A-D
21

Each UART channel in the 654 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See Table 1 and Table 2). The complete register set is shown on Table 9 and Table 10.

0 00 0 0 0 0 00 01 01 10 0 1 1 11 00 01 1 10 1 11 0 1 1 1 1 10 00 01 10 11 X XX
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
3.0 UART INTERNAL REGISTERS
TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES REGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS RHR - Receive Holding Register THR - Transmit Holding Register DLL - Div Latch Low Byte DLM - Div Latch High Byte IER - Interrupt Enable Register ISR - Interrupt Status Register FCR - FIFO Control Register LCR - Line Control Register MCR - Modem Control Register LSR - Line Status Register Reserved MSR - Modem Status Register Reserved SPR - Scratch Pad Register ENHANCED REGISTERS EFR - Enhanced Function Reg Xon-1 - Xon Character 1 Xon-2 - Xon Character 2 Xoff-1 - Xoff Character 1 Xoff-2 - Xoff Character 2 Read/Write Read/Write Read/Write Read/Write Read/Write LCR = 0xBF LCR = 0xBF LCR = 0xBF LCR = 0xBF LCR = 0xBF Read-only Write-only Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Write-only Read-only Write-only Read/Write LCR[7] = 0 LCR[7] = 0 LCR[7] = 0 LCR[7] = 1, LCR 0xBF LCR[7] = 1, LCR 0xBF LCR[7] = 0 LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
FSTAT - FIFO Status Register
Read-only
FSRS# pin is logic 0
22
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
16C550 Compatible Registers 000 000 001 RHR THR IER RD WR RD/WR Bit-7 Bit-7 0/ CTS# Int. Enable Bit-6 Bit-6 0/ RTS# Int. Enable Bit-5 Bit-5 0/ Xoff Int. Enable Bit-4 Bit-4 0/ Sleep Mode Enable Bit-3 Bit-3 Bit-2 Bit-2 Bit-1 Bit-1 Bit-0 Bit-0
RX TX Modem RX Line Data Empty Stat. Stat. Int. Int. Int Int. Enable Enable Enable Enable
010
ISR
RD
FIFOs FIFOs Enabled Enabled
0/ INT Source Bit-5
0/ INT Source Bit-4
INT Source Bit-3
INT INT INT Source Source Source Bit-0 Bit-1 Bit-2
010
FCR
WR
RX FIFO RX FIFO Trigger Trigger
0/
0/
TX FIFO TX FIFO Trigger Trigger
DMA Mode Enable
TX FIFO Reset
RX FIFO Reset
FIFOs Enable
011
LCR
RD/WR
Divisor Enable
Set TX Break
Set Parity
Even Parity
Parity Enable
Stop Bits
Word Word Length Length Bit-1 Bit-0
100
MCR
RD/WR
0/ BRG Prescaler
RTS# DTR# Internal INT Out- Rsvd put Lopback (OP1#) Output Output IR Mode XonAny Enable Enable Control Control ENable (OP2#) 0/ 0/
101
LSR
RD
RX FIFO Global Error
THR & TSR Empty
THR Empty
RX Break
RX Framing Error
RX Parity Error
RX Overrun Error
RX Data Ready
110
MSR
RD
CD# Input
RI# Input
DSR# Input
CTS# Input
Delta CD#
Delta RI#
Delta DSR#
Delta CTS#
111
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor 000 001 DLL DLM RD/WR RD/WR Bit-7 Bit-7 Bit-6 Bit-6 Bit-5 Bit-5 Bit-4 Bit-4 Bit-3 Bit-3 Bit-2 Bit-2 Bit-1 Bit-1 Bit-0 Bit-0 LCR[7] = 1 LCR 0xBF
23

COMMENT LCR[7] = 0 LCR[7] = 0 LCR[7] = 0
See "Receiver" on page15. 4.2 4.3 Transmit Holding Register (THR) - Write-Only Interrupt Enable Register (IER) - Read/Write See "Transmitter" on page13. The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following:
B. C.
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A.

ADDRESS A2-A0 010 EFR 100 101 110 111 XXX
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
Enhanced Registers RD/WR Auto CTS# Enable Auto RTS# Enable Special Char Select
Enable IER [7:4], ISR [5:4], FCR[5:4], MCR[7:5]
Software Flow Cntl Bit-3 Bit-3 Bit-3 Bit-3 Bit-3
Software Flow Cntl Bit-2 Bit-2 Bit-2 Bit-2 Bit-2
Software Flow Cntl Bit-1 Bit-1 Bit-1 Bit-1 Bit-1
Software Flow Cntl Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 LCR=0XBF
XON1 RD/WR XON2 RD/WR XOFF1 RD/WR XOFF2 RD/WR
Bit-7 Bit-7 Bit-7 Bit-7
Bit-6 Bit-6 Bit-6 Bit-6
Bit-5 Bit-5 Bit-5 Bit-5
Bit-4 Bit-4 Bit-4 Bit-4
FSTAT
RD
RXRDYD#
RXRDYC#
RXRDYB#
RXRDYA#
TXRDYD#
FSRS# pin is TXTXTXRDYC# RDYB# RDYA# a logic 0. No address lines required.
4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only
24
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C654 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). B. C. D. E. F.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. Logic 0 = Disable the receive data ready interrupt (default). Logic 1 = Enable the receiver data ready interrupt. IER[1]: THR Interrupt Enable This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the nonFIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is empty when this bit is enabled, an interrupt will be generated. Logic 0 = Disable Transmit Ready interrupt (default). Logic 1 = Enable Transmit Ready interrupt. IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.
* Logic 0 = Disable the receiver line status interrupt (default). * Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
* Logic 0 = Disable the modem status register interrupt (default). * Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
* Logic 0 = Disable Sleep Mode (default). * Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
* Logic 0 = Disable the software flow control, receive Xoff interrupt. (default) * Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details. IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
* Logic 0 = Disable the RTS# interrupt (default). * Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high (if enabled by EFR bit-6).
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A.
25

IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
* Logic 0 = Disable the CTS# interrupt (default). * Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high (if enabled by EFR bit-7). 4.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 11, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 Interrupt Generation:
* LSR is by any of the LSR bits 1, 2, 3 and 4. * RXRDY is by RX trigger level. * RXRDY Time-out is by a 4-char plus 12 bits delay timer. * TXRDY is by TX trigger level or TX FIFO empty. * MSR is by any of the MSR bits 0, 1, 2 and 3. * Receive Xoff/Special character is by detection of a Xoff or Special character. * CTS# is when the remote transmitter toggles the input pin (from low to high) during auto CTS flow control. * RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
4.4.2 Interrupt Clearing:
* LSR interrupt is cleared by a read to the LSR register (LSR bits 1-4 will clear but LSR bit-7 will not clear until
character(s) that generated the interrupt(s) has been emptied or cleared from FIFO).
* RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. * RXRDY Time-out interrupt is cleared by reading RHR. * TXRDY interrupt is cleared by a read to the ISR register or writing to THR. * MSR interrupt is cleared by a read to the MSR register. * Xoff interrupt is cleared by a read to ISR. * Special character interrupt is cleared by a read to ISR register or after next character is received. * RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
26
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
]
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL 1 2 3 4 5 6 7 BIT-5 0 0 0 0 0 0 1 0 ISR REGISTER STATUS BITS BIT-4 0 0 0 0 0 1 0 0 BIT-3 0 1 0 0 0 0 0 0 BIT-2 1 1 1 0 0 0 0 0 BIT-1 1 0 0 1 0 0 0 0 BIT-0 0 0 0 0 0 0 0 1
SOURCE OF INTERRUPT
LSR (Receiver Line Status Register) RXRDY (Receive Data Time-out) RXRDY (Received Data Ready) TXRDY (Transmit Ready) MSR (Modem Status Register) RXRDY (Received Xoff or Special character) CTS#, RTS# change of state None (default)
ISR[0]: Interrupt Status
* Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
* Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 11). ISR[4]: Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s) or a special character. ISR[5]: Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that CTS# or RTS# has changed state from a logic low to logic high. ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable
* Logic 0 = Disable the transmit and receive FIFO (default). * Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
27

FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a `1'.
* Logic 0 = No receive FIFO reset (default) * Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is a `1'.
* Logic 0 = No transmit FIFO reset (default). * Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[3]: DMA Mode Select Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
* Logic 0 = Normal Operation (default). * Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (logic 0 = default, TX trigger level = one) These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 12 below shows the selections. EFR bit-4 must be set to `1' before these bits can be accessed. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 12 shows the complete selections. TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR BIT-7 FCR BIT-6 FCR BIT-5 0 0 1 1 0 0 1 1 0 1 0 1 FCR
BIT-4

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
RECEIVE TRIGGER LEVEL
TRANSMIT TRIGGER LEVEL 8 16 32 56
0 1 0 1 8 16 56 60
28
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received.
BIT-1 0 0 1 1 BIT-0 0 1 0 1 WORD LENGTH 5 (default) 6 7 8
LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2 0 1 1 WORD
LENGTH
STOP BIT LENGTH (BIT TIME(S)) 1 (default) 1-1/2 2
5,6,7,8 5 6,7,8
LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 13 for parity selection summary below.
* Logic 0 = No parity. * Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
* Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format (default).
* Logic 1 = EVEN Parity is generated by forcing an even number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format.
29

LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
* LCR BIT-5 = logic 0, parity is not forced (default). * LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
* LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data. TABLE 13: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, "1" Forced parity to space, "0"
LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a "space', logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
* Logic 0 = No TX break condition. (default) * Logic 1 = Forces the transmitter output (TX) to a "space", logic 0, for alerting the remote receiver of a line
break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable.
* Logic 0 = Data registers are selected. (default) * Logic 1 = Divisor latch registers are selected.
4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output.
* Logic 0 = Force DTR# output to a logic 1 (default). * Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
* Logic 0 = Force RTS# output to a logic 1 (default). * Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved OP1# is not available as an output pin on the 654. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
30
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# signal during internal loopback mode. INTSEL pin must be set to a logic zero during 68 mode.
* Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During loopback mode, it sets
OP2# internally to a logic 1.
* Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During loopback mode, it sets OP2# internally
to a logic 0. TABLE 14: INT OUTPUT MODES
INTSEL PIN 0 0 1 MCR BIT-3 0 1 X INT A-D OUTPUTS IN 16 MODE Three-State Active Active
MCR[4]: Internal Loopback Enable
* Logic 0 = Disable loopback mode (default). * Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
* Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default). * Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and the 654 is programmed to use the Xon/Xoff flow control. MCR[6]: Infrared Encoder/Decoder Enable
* Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default) * Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output will be a logic 0 during idle data conditions. MCR[7]: Clock Prescaler Select
* Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
* Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth. 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an error is in the RHR. LSR[0]: Receive Data Ready Indicator
* Logic 0 = No data in receive holding register or FIFO (default). * Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
31

LSR[1]: Receiver Overrun Flag
* Logic 0 = No overrun error (default). * Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[2]: Receive Data Parity Error Tag
* Logic 0 = No parity error (default). * Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Tag
* Logic 0 = No framing error (default). * Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. LSR[4]: Receive Break Tag
* Logic 0 = No break condition (default). * Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, "mark" or logic 1. LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag
* Logic 0 = No FIFO error (default). * Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 4.9 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag
* Logic 0 = No change on CTS# input (default). * Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
32
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
MSR[1]: Delta DSR# Input Flag
* Logic 0 = No change on DSR# input (default). * Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag
* Logic 0 = No change on RI# input (default). * Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[3]: Delta CD# Input Flag
* Logic 0 = No change on CD# input (default). * Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.10 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. 4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the baud rate:
* Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also. 4.12 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting.
33

EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3 CONT-3 0 0 1 0 1 X X X 1 EFR BIT-2 CONT-2 0 0 0 1 1 X X X 0 EFR BIT-1 CONT-1 0 X X X X 0 1 0 1 EFR BIT-0 CONT-0 0 X X X X 0 0 1 1 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL No TX and RX flow control (default and reset) No transmit flow control Transmit Xon1, Xoff1 Transmit Xon2, Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 No receive flow control Receiver compares Xon1, Xoff1 Receiver compares Xon2, Xoff2 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 No transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.
* Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7are set to a logic 0 to be compatible with ST16C550 mode (default).
* Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
* Logic 0 = Special Character Detect Disabled (default). * Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= `10') then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= `01') then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt, if enabled via IER bit-5.

0 1 0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
1
1
1
1
1
1
0
1
1
34
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS deasserts to a logic 1 at the next upper trigger level/hysteresis level. RTS# will return to a logic 0 when FIFO data falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (logic 0) before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
* Logic 0 = Automatic RTS flow control is disabled (default). * Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable Automatic CTS Flow Control.
* Logic 0 = Automatic CTS flow control is disabled (default). * Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0. 4.13 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 8. 4.14 FIFO Status Register (FSTAT) - Read/Write This register is applicable only to the 100 pin QFP ST16C654. The FIFO Status Register provides a status indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the FSTAT register are placed on the data bus when the FSRS# pin (pin 76) is a logic 0. Also see FSRS# pin description. FSTAT[3:0]: TXRDY# A-D Status Bits Please see Table 5 for the interpretation of the TXRDY# signals. FSTAT[7:4]: RXRDY# A-D Status Bits Please see Table 5 for the interpretation of the RXRDY# signals.
35

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
TABLE 16: UART RESET CONDITIONS FOR CHANNELS A-D
REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0xFF RESET STATE Logic 1 Logic 0 Logic 1 Logic 1 Logic 1 Logic 0 ST16C654 = Three-State Condition ST16C654D = Logic 0 Three-State Condition (68 mode, INTSEL = 0) RESET STATE
SPR EFR XON1 XON2 XOFF1 XOFF2 FSTAT I/O SIGNALS TX IRTX RTS# DTR# RXRDY# TXRDY# INT
IRQ#
36
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
ABSOLUTE MAXIMUM RATINGS
Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation 7 Volts GND-0.3 V to 7 V -40o to +85oC -65o to +150oC 500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%)
Thermal Resistance (64-TQFP) Thermal Resistance (68-PLCC) Thermal Resistance (100-QFP) theta-ja = 49oC/W, theta-jc = 10oC/W theta-ja = 39oC/W, theta-jc = 17oC/W theta-ja = 45oC/W, theta-jc = 12oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85 OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V
LIMITS 3.3V MAX MIN -0.3 2.4 -0.3 2.0 0.6 VCC 0.8 VCC LIMITS 5.0V MAX MIN -0.5 3.0 -0.5 2.2 0.6 VCC 0.8 VCC 0.4 0.4 2.4 2.0 10 10 5 3 100 10 10 5 6 200
SYMBOL
PARAMETER
UNITS
VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL IIH CIN ICC ISLEEP
Clock Input Low Level Clock Input High Level Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Input Pin Capacitance Power Supply Current Sleep Current
V V V V V V V V uA uA pF mA uA See Test 1 IOL = 6 mA IOL = 4 mA IOH = -6 mA IOH = -1 mA
37

CONDITIONS
SHHOVD HOLKZ HWDWV FLJR O WD HOGL VWXSQL ';5 GQD &;5 %;5 $;5 RVO$ '6& GQD &6& %6& $6& :2, 52, '' $$ WQHUU XF S H H O 6 H ] LP LQLP RW HWDWV '1* U R & & 9 WD \GDHWV QLDPHU VWXSQL JQ LZR OORI HK7 WVH7
AC ELECTRICAL CHARACTERISTICS TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97
SYMBOL PARAMETER LIMITS 3.3 MAX MIN 20 8 10 5 66 50 50 45 0 40 50 20 15 10 15 10 30 0 30 50 15 10 10 15 10 5 5 50 30 50 35 20 LIMITS 5.0 MIN 20 24 MAX ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50 35 35 1 ns ns ns Bclk 100 pF load 100 pF load 100 pF load
TO
Write Data Setup (68 mode) Write Data Hold (68 Mode) CS# De-asserted to R/W# De-asserted (68 Mode) CS# Strobe Width (68 Mode) CS# Cycle Delay (68 Mode) Delay From IOW# To Output Delay To Set Interrupt From MODEM Input Delay To Reset Interrupt From IOR# Delay From Stop To Set Interrupt
20 10 10
15 10 10
TWDO TMOD TRSI TSSI
50 50 50 1
38

Data Disable Time (68 mode)

CLK OSC TRD TDY TRDV TDD TWR TDY TDS TDH
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
5.5V
UNIT CONDITIONS
Clock Pulse Duration Crystal/External Clock Frequency Address Setup Time (16 Mode) Address Hold Time (16 Mode) Chip Select Width (16 Mode) IOR# Strobe Width (16 Mode) Read Cycle Delay (16 Mode) Data Access Time (16 Mode) Data Disable Time (16 Mode) IOW# Strobe Width (16 Mode) Write Cycle Delay (16 Mode) Data Setup Time (16 Mode) Data Hold Time (16 Mode) Address Setup (68 Mode) Address Hold (68 Mode) R/W# Setup to CS# (68 Mode) Data Access Time (68 mode)
+:57
+':7
6:57
6':7
+'57
'6&7
$'57
+'$7
6'$7
/6&7
7 7 7
AS
AH CS
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
AC ELECTRICAL CHARACTERISTICS TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97
SYMBOL PARAMETER LIMITS 3.3 MAX MIN 200 100 8 24 175 1 175 175 8 40 1 216-1 40 1 216-1 8 LIMITS 5.0 MIN MAX 200 100 24 175 1 175 175 8
TO
5.5V
UNIT CONDITIONS
TRRI TSI TINT TWRI TSSR TRR TWT TSRT TRST N Bclk
Delay From IOR# To Reset Interrupt Delay From Start To Interrupt Delay From Initial INT Reset To Transmit Start Delay From IOW# To Reset Interrupt Delay From Stop To Set RXRDY# Delay From IOR# To Reset RXRDY# Delay From IOW# To Set TXRDY# Delay From Center of Start To Reset TXRDY# Reset Pulse Width Baud Rate Divisor Baud Clock
ns ns Bclk ns Bclk ns ns Bclk ns Hz
16X of data rate
FIGURE 14. CLOCK TIMING
39

100 pF load
./& &62
./& .&2/& /$15(7;(
2%#
ataD dilaV
''T 9 '5T ''T
'5T <'T
+$T
6&T 6$T
sserddA dilaV
HW DW V I R
HJQ DK &
'207
H YL W F $ H YL W F $ H YL W F $ 5 2,
,65
H YL W F $ H YL W F $
'20 7
HW DW V I R HJQ DK & HW DW V I R HJQ DK &
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D
7
H YL W F $
HW DW V I R
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D
40
ataD dilaV
9 '5T
7D-0D
#ROI
'5T
#SC
+$T 6&T 6$%
sserddA dilaV
7A-0A
,5
7 1,
'207
56' 67& '&
57' HJQ DK & HW DW V I R HJQ DK & 675
2' : 7
: 2, H YL W F $ : 2,
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0

GDH5
D WD' GLO D9
+'57 +:57
'6&7
+'$7
VVHUGG$ GLO D9
HWLU:
DWD' GLOD9
+'7 6'7 +'7
5:7 <'7
+$7
6&7 6$7
VVHUGG$ GLOD9

REV. 5.0.0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D
41
D WD' GLO D9
$'57
''
:5
6:57
6&
/6&7 6'$7
VVHUGG$ GLO D9
$$
DWD' GLOD9
6'7
''
:2,
5:7
6&
+$7 6&7 6$7
VVHUGG$ GLOD9
$$
0)1 ;5
R R7
R R7
\GDH5 DWD' HYLWF$
#$$7
\GDH5 DWD' HYLWF$
#$$7
5+5 QL H W \%
RSS7
5+5 QL HW\%
RSS7
''
''
HWLU:
DWD' GLOD9
+': 7 +:57 '6&7
VVHUGG$ GLOD9
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D
+'$7
42
5+5 IR WXR DWDG JQLGDH5 52,
R R7
\GDH5 DWD' HYLWF$
#$$7
<'5;5
5+5 QL HW\%
RSS7
71,
WL% SRW6
''
WL% WUDW6
;5
DWD' GLOD9
6':7
''
:5
6:57
6&
/6&7 6'$7
VVHUGG$ GLOD9
$$
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0

$0' 7 1,;5
55 7
,55 7
seitpmE OFIF
tuoemiT ataD XR ro lev eL reggirT XR ot pu sllif OFIF XR
lev eL reggirT XR wol eb spord OFIF XR
7 7D:0D 6 7 7D:0D 6 7 7D:0D 6 7 7D:0D 6
2) ,) QR1 ;7

REV. 5.0.0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D
5+7 HKW RWQL GHGDRO VL DWDG QHKZ U R GDH U V L 56, HKW Q H KZ G HUDHOF VL 71,
5+7 RWQL DWDG JQLGDR/
7:7
7567 ,5:7
GD HU VL 56,
''
GD HU VL 56,
'' WL% SRW6
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D
43
2),) ;5 IR WXR DWDG JQLGDH5 52,
OFIF XR ni devi ec eR si etyB tsriF <'5;5
566%
71,
,66 7
WL% SRW6 7 7D:0D 6
7D:0D
'' $
WL% WUDW6
;5
#WOI
7:7
7:7
#YDRXT
7567 ,5: 7 7567 ,5:7
*TNI
GD HU VL 56,
'' WL% WUDW6
GHOEDQH @>5(, JQLGDROQ8
XT
$0 '2),);5
55 T
,55 T
VHLWSP( 2),)
OHYH/ UHJJLU7 ;5 ZROHE VSRUG 2),) ;5
T
'' S
T
'' S T '' S
T
'' S
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D
44
)OFIF XR fo tuo atad gnidaeR(
52,
<'5;5
566 T
WXRHPL7 DWD' ;5 UR OHYH/ UHJJLU7 ;5 RW SX VOOLI 2),) ;5
71,
,66 T
''
T
'' S
'' S
tiB tratS
;5
tiB potS
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0

$0';7
7 :7
OOX) 2),) ;7
,5 :7
2),) QL QRLWDFRO \WSPH WVDHO W$ OHYHO UHJJLUW ZROHE VSRUG 2),) ;7
GDH5 56, 7 '' 6 GHWWLPVQDU7 HW\% DWD' WVD/
,67
7567
7 '' 6 7 '' 6
7 '' 6

REV. 5.0.0
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D
$0' ;7
OHYHO UHJJLUW HKW RW SX VOOLI 2),) ;7 QHKZ UR GDHU VL 56, HKW QHKZ GHUDHOF VL 71, 2),) RWQL DWDG JQLGDR/
\WSP( 2),) ;7
756
OHYHO UHJJLUW ZROHE VSRUG 2),) ;7
,5 : 7
7
GDHU VL 56, 7 '' 6 7 '' 6 7
,6
7 7 '' 6 7 '' 6
7 '' 6 GHWWLPVQDU7 HW\% DWD' WVD/
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
45
OHYHO UHJJLUW RW SX VOOLI 2),) ;7 QHKZ UR GDHU VL 56, HKW QHKZ GHUDHOF 71, 2),) RWQL DWDG JQLGDR/
:2,
<'5;7
OHYHO UHJJLUW RW SX VOOLI 2),) ;7
71,
GDH5 56, '' 7 '' 6 7 '' 6 WL% SRW6 WL% WUDW6 GHOEDQH @>5(, JQLGDROQ8
;7
:2,
7:
7 2),) ;7 QL DWD'
<'5;7
OHYHO UHJJLUW RW SX VOOLI 2),) ;7
71,
GDHU VL 56, 7 '' 6 WL% SRW6 WL% WUDW6 \WSP( 2),) ;7 GHOEDQH @>5(, JQLGDROQ8
;7
PACKAGE DIMENSIONS 64 LEAD THIN QUAD FLAT PACK (10 x 10 x 1.4 mm TQFP)
D D1 48 33

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
49
32
D1
D
64
17
1
16
B A2 e C
A S eating P lane A1 L
Note: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.055 0.002 0.053 0.007 0.004 0.465 0.390 MAX 0.063 0.006 0.057 0.011 0.008 0.480 0.398 MILLIMETERS MIN 1.40 0.05 1.35 0.17 0.09 11.80 9.90 MAX 1.60 0.15 1.45 0.27 0.20 12.20 10.10
0.020 BSC 0.018 0 0.030 7
0.50 BSC 0.45 0 0.75 7
46
ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
D D1 45 x H2 2 1 68 45 x H1 C
Seating Plane A2
D
D1
D3
R D3 A1 A
Note: The control dimension is the inch column
INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.985 0.950 0.890 MAX 0.200 0.130 ---. 0.021 0.032 0.013 0.995 0.958 0.930 MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 25.02 24.13 22.61 MAX 5.08 3.30 --0.53 0.81 0.32 25.27 24.33 23.62
0.800 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045 1.07 1.07 0.64
20.32 typ. 1.27 BSC 1.42 1.22 1.14
47

B1 B D2 e

ST16C654/654D 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
100 LEAD PLASTIC QUAD FLAT PACK (14 mm x 20 mm QFP, 1.95 mm Form)
D D1 80 51
81
50
E1
E
100
p
31
1
30
A2 A Seating Plane A1
B e C
L
Note: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D D1 E E1 e L MIN 0.102 0.002 0.100 0.009 0.004 0.931 0.783 0.695 0.547 MAX 0.134 0.014 0.120 0.015 0.009 0.951 0.791 0.715 0.555 MILLIMETERS MIN 2.60 0.05 2.55 0.22 0.11 23.65 19.90 17.65 13.90 MAX 3.40 0.35 3.05 0.38 0.23 24.15 20.10 18.15 14.10
0.0256 BSC 0.029 0 0.040 7 0.73 0
0.65 BSC 1.03 7
48
ST16C654/654D
REVISION HISTORY
DATE REVISION DESCRIPTION
October 2003
Rev 5.00
Changed to standard style single-column format. Text descriptions were clarified and simplified (eg. DMA operation, FIFO mode vs. Non-FIFO mode operations etc). Clarified timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing symbols. Added TCS, TRWS and T RST.Renamed FIFORdy register to FSTAT register.
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet October 2003. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 49

NOTICE
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
GENERAL DESCRIPTION................................................................................................. 1
FEATURES ..................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. ST16C654 BLOCK DIAGRAM ........................................................................................................................................... 1 FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE ....................................................................... 2 FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND TQFP PACKAGES ............................................... 3 ORDERING INFORMATION ................................................................................................................................ 3
PIN DESCRIPTIONS ......................................................................................................... 4
1.0 PRODUCT DESCRIPTION .................................................................................................................... 8 2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 9
2.1 CPU INTERFACE ............................................................................................................................................. 9
FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ................................................................... 9
3.0 UART INTERNAL REGISTERS ........................................................................................................... 22
TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 22 TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1....................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24 4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 24 4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 25

2.16 2.17
ST16C654/654D
REV. 5.0.0
TABLE OF CONTENTS
2.2 DEVICE RESET .............................................................................................................................................. 10 2.3 CHANNEL SELECTION ................................................................................................................................. 10
TABLE 1: CHANNEL A-D SELECT IN 16 MODE ................................................................................................................................. 10 TABLE 2: CHANNEL A-D SELECT IN 68 MODE ................................................................................................................................. 10
2.4 CHANNELS A-D INTERNAL REGISTERS .................................................................................................... 11 2.5 INT OUPUTS FOR CHANNELS A-D .............................................................................................................. 11 2.6 DMA MODE .................................................................................................................................................... 11
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D ......................................................................................... 11 TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D ................................................................................................. 11
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 12
FIGURE 5. TYPICAL OSCILLATOR
CONNECTIONS...............................................................................................................................
12
2.8 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 12
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D ........................................................... 12
2.9 TRANSMITTER ............................................................................................................................................... 13
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 13 FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ..................................................................................................................... 13 TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 13 2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 14 2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 14 FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14 FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.10 RECEIVER .................................................................................................................................................... 15
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 15 FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 15
2.11 AUTO RTS HARDWARE FLOW CONTROL ............................................................................................... 16 2.12 AUTO CTS FLOW CONTROL ..................................................................................................................... 16
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 16 FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 17 TABLE 7: AUTO RTS/CTS FLOW CONTROL .................................................................................................................................... 17
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 18 2.14 SPECIAL CHARACTER DETECT ............................................................................................................... 18
TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18
2.15 INFRARED MODE ........................................................................................................................................ 19
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 19
SLEEP MODE WITH AUTO WAKE-UP ...................................................................................................... 20 INTERNAL LOOPBACK .............................................................................................................................. 20
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 21
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
I
ST16C654/654D
REV. 5.0.0
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 27
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 27 TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 29 4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 30
TABLE 13: PARITY
SELECTION ........................................................................................................................................................ 30
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 31
TABLE 14: INT OUTPUT MODES ..................................................................................................................................................... 31
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 4.12 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 34
4.13 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 35 4.14 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 35
TABLE 16: UART RESET CONDITIONS FOR CHANNELS A-D.................................................................................................. 36
ABSOLUTE MAXIMUM RATINGS...................................................................................37 TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: 15%) 37 ELECTRICAL CHARACTERISTICS ................................................................................37
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................37 AC ELECTRICAL CHARACTERISTICS ..............................................................................................................38 TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V.........................38
FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. FIGURE 23. FIGURE 24. FIGURE 25. CLOCK TIMING............................................................................................................................................................. 39 MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 40 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D.................................................................................... 40 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 41 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 41 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 42 RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 42 TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 43 RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 43 RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 44 TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 45 TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 45
PACKAGE DIMENSIONS .................................................................................................................................46 REVISION HISTORY.......................................................................................................................................49 TABLE OF CONTENTS ............................................................................................................I
II

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